The present invention relates to a ferroelectric non-volatile memory device and, more particularly, to a ferroelectric non-volatile memory device having a ferroelectric capacitor connected to the gate of a MOS (Metal Oxide Semiconductor) or MIS (Metal Insulator Semiconductor) field effect transistor.
The formation of a junction between a semiconductor and a ferroelectric can create, depending on the polarization direction of the ferroelectric, a state in which electrons are induced to the semiconductor surface, or a state in which holes are induced. Attempts have already been made to manufacture non-volatile memory devices which hold memory contents even after power-off operation by using a ferroelectric for the gate insulator film of a MOS field effect transistor and making the two states correspond to xe2x80x9cOxe2x80x9d and xe2x80x9clxe2x80x9d. However, no practical devices have been realized yet. Devices with this structure are difficult to manufacture for the following reason. If a semiconductor and ferroelectric are joined to each other, an interface state is formed to capture electrons and holes. This stops the flow of a necessary current through the source-drain path of a field effect transistor.
To solve this problem, an MFIS (M: Metal or Conductor, F: Ferroelectric, I: Insulator, S: Semiconductor) structure and an MFMIS structure are proposed. In the MFIS structure, a dielectric (paraelectric) film such as a silicon dioxide (SiO2) film that hardly forms any interface state with a semiconductor is inserted between a ferroelectric film and a semiconductor substrate. In the MFMIS structure, a conductive layer is further sandwiched between a ferroelectric film and a dielectric film. However, if the series structure of ferroelectric and dielectric films is used as the gate insulator film of the field effect transistor, new problems arise: (1) the data write-in voltage rises, and (2) the data retention time is shortened. These problems will be explained.
The rise in the write-in voltage will be explained by exemplifying a structure. In this case, the semiconductor substrate is made of Si, the ferroelectric film is made of lead zirconate titanate (PZT: PbZr1-xTixO3), and the dielectric film is made of SiO2. The MFIS structure may be adopted as the structure of the gate electrode, but the MFMIS structure is adopted for these materials in order to prevent mutual diffusion of Pb atoms in the PZT film and Si atoms in the SiO2 film. The relative dielectric constant of SiO2 is 3.9. The relative dielectric constant of PZT takes a value ranging from 200 to 600 depending on the composition ratio of Zr and Ti, and is assumed to be 390 for descriptive convenience. In general, the thickness of the SiO2 film is {fraction (1/10)} that of the PZT film.
Since the capacitance of the capacitor is proportional to the relative dielectric constant and inversely proportional to the film, the ferroelectric capacitor and the dielectric capacitor have a capacitance ratio of 10:1. When two capacitors are series-connected, and a voltage is applied to them, the voltage applied to each capacitor is inversely proportional to the capacitance of the capacitor. The voltage applied to the ferroelectric capacitor is {fraction (1/10)} that to the dielectric capacitor, i.e., {fraction (1/11)} the total voltage. Assume that an MFS structure in which the PZT film is directly deposited on the Si substrate is formed, and the polarization of the film can be inverted at 5V. An MFMIS structure formed at the same film thickness requires a high voltage of 55V for polarization inversion.
The short data retention time will be explained with reference to FIGS. 9A and 9B. The equivalent circuit of the MFMIS structure is shown in FIG. 9A. In FIG. 9A, reference symbol CF denotes a ferroelectric capacitor; CI, a dielectric capacitor. In this case, the whole semiconductor is kept at the ground potential without considering the capacitance of the depletion layer of the semiconductor.
If a voltage V is applied to an upper electrode, voltages VF and VI are applied to the two capacitors. The voltages VF and VI satisfy
VF+VI=Vxe2x80x83xe2x80x83(1) 
Let xc2x1Q be the amount of electric charges appearing in the upper and lower electrodes of the ferroelectric capacitor. As shown in FIG. 9A, the amount xc2x1Q of electric charges also appears in the upper and lower electrodes of the dielectric capacitor on a condition that the net electric charges of an intermediate portion between the two capacitors must be 0. Since the dielectric capacitor has the relation of Q=CIVI, a substitution of this relation into equation (1) yields:
Q=CI(Vxe2x88x92VF)xe2x80x83xe2x80x83(2) 
The relationship between Q and VF of the ferroelectric capacitor exhibits hysteresis, as shown in FIG. 9B. This relation given by equation (2) is overlapped in FIG. 9B to obtain a straight line in FIG. 9B. An intersection between the lines represents a voltage applied to the ferroelectric and the amount of electric charges appearing in the capacitor electrode. A point A in FIG. 9B represents Q and VF when the voltage is kept at V after a large voltage is positively applied, and a point B represents Q and VF when the voltage is kept at V after a large voltage is negatively applied.
If the voltage is reset to 0 after a large voltage is positively applied, Q and VF of the ferroelectric capacitor change to a point C in FIG. 9B, and the polarization direction and electric field direction are opposite. In other words, if the gate voltage is reset to 0 to hold data after data is written by applying a positive voltage to the gate electrode of a field effect transistor having the MFIS or MFMIS gate structure, an electric field opposite to the polarization direction is applied to the ferroelectric, and the remanent polarization disappears within a short time. Particularly when the capacitance of the series-inserted dielectric capacitor is small, the magnitude of an inverse electric field comes close to the coercive electric field (electric field necessary for resetting the polarization to 0) of the ferroelectric, and the polarization retention time becomes very short.
The short retention time may not be ignored not only in the MFIS and MFMIS structures but also in the MFS structure. Even if an interface with low trapping state density can be formed between a ferroelectric film and a semiconductor film, and a field effect transistor having a fine MFS gate structure can be manufactured, the ferroelectric capacitor and the capacitance of a depletion layer formed in the semiconductor surface form a series capacitor to pose almost the same problem as shown in FIG. 9B.
For this reason, a conventional non-volatile memory device using a ferroelectric for the gate insulator film of a MOS field effect transistor must adopt the MFIS or MFMIS structure so as not to form an interface state between a semiconductor substrate and the ferroelectric film. However, this type of structure increases the data write-in voltage and shortens the data retention time.
It is an object of the present invention to provide a ferroelectric non-volatile memory device capable of decreasing the data write-in voltage and prolonging the data retention time in a memory cell structure using a ferroelectric capacitor.
According to the present invention, there is provided a ferroelectric non-volatile memory device comprising a MOS or MIS cell transistor, and two ferroelectric capacitors which are connected to a gate electrode of the transistor and have substantially the same remanent polarization, wherein data is stored by polarizing ferroelectric thin films of the capacitors in opposite directions with respect to the gate electrode of the transistor, and a selector transistor is formed on one side of one capacitor.
According to the present invention, there is provided a ferroelectric non-volatile memory device comprising a MOS or MIS cell transistor, two ferroelectric capacitors each of which has one terminal connected to a gate electrode of the cell transistor and has substantially the same remanent polarization, and a selector transistor connected to the other terminal of one of the ferroelectric capacitors, wherein data is stored by polarizing ferroelectric thin films of the capacitors in opposite directions with respect to the gate electrode of the cell transistor.
Preferable aspects of the present invention include the following arrangements:
(1) One of the capacitors has one terminal connected to the gate electrode of the cell transistor and the other terminal connected to a bit line via the selector transistor, the other capacitor has one terminal connected to the gate electrode of the cell transistor and the other terminal connected to a plate line, and the gate electrode of the selector transistor is connected to a word line.
(2) In arrangement (1), the source of the cell transistor is grounded, and its drain is connected to the word line.
(3) In arrangement (1), the source of the cell transistor is grounded, and its drain is connected to the bit line.
According to the present invention, a memory cell structure is formed by connecting two ferroelectric capacitors having almost the same remanent polarization to the gate electrode of a MOS or MIS cell transistor. Data is stored in accordance with the polarization direction and remanent polarization of the ferroelectric thin film. In storing data, the ferroelectric thin films of the capacitors are polarized in opposite directions with respect to the gate electrode of the cell transistor. Electric charges generated upon polarization of the ferroelectric thin film are not induced to the semiconductor surface of the channel region of the cell transistor.
In this case, since the voltage is directly applied to the ferroelectric thin film, the data write-in voltage can be decreased. Since the internal electric fields of the two ferroelectric capacitors are 0 regardless of whether data is held in a xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d state, the data retention time can be prolonged. That is, in a memory cell structure using the ferroelectric capacitors, the data write-in voltage can be decreased, and the data retention time can be prolonged.
In addition, since the selector transistor is connected to a side of one ferroelectric capacitor opposite to the cell transistor, an unselected cell can be prevented from being influenced by the write-in voltage.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.